Modeling Of Finite State Machines
A designer should consider the different aspects of an
FSM before attempting to write a model. A well-written model is essential for a
functionality correct circuit that meets requirements in the most optimal
manner. A badly written model may not meet either criteria. For this reason, it
is important to fully understand FSMs and to be familiar with the different HDL
modeling issues.
The Finite State Machine
A FSM is any circuit specifically designed to sequence
through specific patterns of states in a predetermined sequential manner, and
which conforms to the structure shown in fig below. A state is represented by
the binary value held on the current register. The FSM structure consists of
three parts and may, or may not, be reflected in the structure of them HDL code
that is used to model it.
The State Table and State Diagram
A state diagram is a graphical representation of a state
machine’s sequential operation and is often supported as a direct input to
commercial synthesis tools from which synthesized circuits and HDL simulation
models are generated. Whether to use a state diagram or HDL entry method is
often a choice for the designer, provided the tools are available.
The structure of a
state machine can take one of three forms, fig 11.3, and consists of a combinational
"Next State Logic" block, a sequential "Current State
Register" block, and an optional combinational "Output Logic "
block. Output logic is not needed if the outputs only come direct from the
state register flip-flops. The current state is not stored in flip-flops;
latches would cause state oscillations when transparent. The next state and output
logic blocks may contain additional sequential logic, inferred from within the body
of the model, but is not considered part of the state machine. A state machine
can only be in one state at any given time, and each active transition of the
clock causes it to change from its
current state to the next as defined by the next state logic.
A state machine with n state flip-flops has
2n possible binary numbers that can be used to represent states. Often, not all
2n numbers are needed, so the unused ones should be designed not to occur
during normal operation. A state machine with five states, for example,
requires a minimum of three flip-flops in which case there are (8 - 5 = 3) unused
binary numbers.
module
FSM1_BAD (Clock, SlowRAM, Read, Write);
input Clock,
SlowRAM;
output Read,
Write;
reg Read ,
Write;
always@(posedge
Clock)
begin:
SEQ_AND_COMB
parameter
ST_Read = 0, ST_Write = 1, Delay =2;
integer
State;
case (State)
ST_Read:
begin
Read = 1;
Write = 0;
State =
ST_Write;
end
ST_Write:
begin
Read = 0;
Write =1;
if(SlowRAM =
= 1)
State
=ST_Dealy ;
else
State =
ST_Read ;
end
ST_Delay :
begin
Read = 0;
Write =0;
State
=ST_Read;
end
endcase //
Because there is no default and therefore no new value for Read
// and
Write, the 2 extra outputs flip-flops will also have
// feedback
logic around them
end
endmodule
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