### Introduction to Sequential Circuits

Introduction
Flip-flop is a memory element which change its condition based on clock signal. Clock is a square waveform. The clock pulses determine when computational activity (next state of the system) will occur. The output of this activity is function of the external inputs and the current state (sometimes called previous state) of the system.
Pulse triggered
Latch
ON when clock is at 1 level, OFF when clock is at 0 level (or in the opposite)
Edge triggered
Flip-flop
Positive edge triggered (ON when clock changes from 0 to 1, OFF=other time)
Negative edge triggered (ON when clock changes from 1 to 0, OFF=other time)
Latches
Latches are said to be level sensitive devices.
They are asynchronous logic circuits since they are pulse triggered.
We will study since they are the basic building blocks of flip flops.
Two types of latches:
Set-Reset Latches (SR Latches).
Data Latches (D Latches).
SR Latches
Output has complement: Q and Q’
When Q HIGH, latch in SET condition
When Q LOW, latch in RESET condition
Two types:
Active high (called SR latch).
Active  high (called S’R’ latch).
Procedure:
Latch
After installing the 7475 IC in the board we verified the operation of the D latch by connecting the IC as follows:

D type FF

To verify the operation of the D-FF, we connected the 7474 IC as follows:

JK type FF
After installing the 7476 IC, we verify the proper operation of each FF by connecting the IC as follows:

Sequential circuit application (Circulating shift register)
a.     Circulating shift register using D-FF:
We constructed the circuit using two 7474 ICs, to get the Ring shift register.

For the circuit to work properly we set:
CLR to 1, PRE1 to 0, PRE2 = PRE3 = PRE4 = 1
With each rising edge of the clock, the data will circulate as shown in the truth table below:

a.     Tail ring counter using JK-FF

A switch tail ring counter is a circular shift register with the complimented e last flip flop connected to the input of the first flip flop.
A 4-bit shift register connected as a ring counter is shown below:

After Pre’ and Clr’ are set to high, the four leds are all on, because it is active low. After the first clock, the output (1) of the last FF becomes the K input of the first FF, and the complimented output of the last FF (0) becomes the J input of the first FF, causing the first FF to the Reset state and the first led will turn off.
After the second clock, the output (0) of the 1st FF will enter the second FF leading it to the reset state, and the 2nd Led will turn off. The same thing happens for the 3rd and 4th clocks.
On the 5th clock, the output (0) of the last FF becomes the K input of the first FF, and the complimented output of the last FF (1) becomes the J input of the first FF, causing the first FF to the set state and the first led will turn on.
On the 7th clk, the output (1) of the 1st FF will enter the 2nd FF leading it to the set state and the 2nd FF will turn on. The same happens for the 8th clk, and then the loop starts all over again.

The invalid states are: 0010, 0100, 0101, 0110, 1001, 1010, 1011, 1101.